1. Field of the Invention
This invention relates to high resolution generators for digital display units and more particularly to a video output system for such units.
2. Description of the Prior Art
New applications are being increasingly found for display units coupled to a data processing system. Such display units may be custom made for such purposes or may be formed of conventional commercial television sets. In either case, the information displayed is usually of the nature of characters formed of a dot matrix where the display unit employs a raster scan mode. Each horizontal line is divided into a number of discrete points or areas called picture elements (PELS) or pixels. A fraction of such picture elements per line is not employed for information display but is that portion of the scan time required for horizontal retrace and synchronization of the horizontal oscillator.
As the display screen is scanned, the dot matrix characters are formed by character generation circuits that control the modulation of the electron beam (in the case of CRT displays), individual circuits of which are selected by character codes that are stored in a memory. This code store can be a shift register with exactly the same number of cells as there are character positions on the display screen, or it may be a random access memory.
In some display units, 25 to 30 complete scans of all the lines making up the display are made per second. Thus, each portion of a character being displayed is on display 25 to 30 times a second for a brief period and this can cause an apparent flickering. The flickering problem is normally solved by refreshing or redrawing all the lines in the display in two consecutive interlaced scans. A "half-scan" is redrawn or refreshed in half the time. Because of the 2:1 interlace between the two half-scans, if a horizontal line is drawn in one half-scan and is adjacent to a line drawn in the next half-scan, the two form a line on the display screen with reduced flicker because, in essence, it is written twice as often. Applying this knowledge, a 6.times.8 dot matrix character can be displayed on a 12.times.16 dot matrix, by displaying each dot in the 6.times.8 matrix four times. This reduces the flicker considerably, as the character now seems to be written 50 to 60 times a second, instead of 25 to 30 times. However, this results in an objectionable feature in that diagonal lines have a ragged appearance and "included" corners are not provided. This ragged appearance becomes more pronounced if the characters are displayed with a finer resolution than that with which they are stored in the character generator store.
A particular solution to the flicker and ragged character appearance is provided by the Seitz et al U.S. Pat. No. 4,119,954 which is directed toward a display system adapted for commercial video monitors with interlaced scans wherein circuitry is provided to sense the lack of an information bit in areas adjacent to dot character areas, which areas form a diagonal, and to fill in those diagonal adjacent areas so as to thereby give the displayed character a smooth appearance. In the Seitz et al patent, the information is supplied serially in digital form to a digital-to-analog converter for presentation of the final composite video signal. The serial nature of such a system presents a time lag when it is desired to display a number of characters in a relatively short period of time.
Such time lag can be overcome by the implementation of the algorithm of the Seitz et al patent by parallel circuitry. Furthermore, the character code supplied to the code generation circuitry should be arranged in sequence for presentation to that circuitry and to this end, line buffering or storage is required.
It is, then, an object of the present invention to provide an improved information display unit which is flicker-free and in which displayed characters do not have a ragged appearance.
It is another object of the present invention to provide a flicker-free display unit for digital information which displays relatively smooth characters with reduced time lag in the display of those characters.
It is still another object of the present invention to provide a high resolution character generation circuitry for a display unit, which display unit is provided with line buffering for the presentation of character codes to the generation circuitry in consecutive sequences.